module rom (
	input wire[5:0] addr,
	input wire ce,
	output reg[31:0] inst
);

	reg[31:0] rom[0:63];		// 64 个 32 bit 的 rom

	initial $readmemh ("rom.data", rom);	// init rom from file

	always @(*) begin
		if (ce == 0) begin
			inst <= 0;
		end
		else begin
			inst <= rom[addr];
		end
	end

endmodule